ADT7481ARMZ-1RL【PDF 14/20 页】IC SENSOR TEMP 2CH ALARM 10MSOP

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ADT7481

http://onsemi.com

The number of data bytes that can be transmitted over the

serial bus in a single read or write operation is limited only

by what the master and slave devices can handle.

When all data bytes have been read or written, stop

conditions are established. In write mode, the master will

pull the data line high during the tenth clock pulse to assert

a stop condition. In read mode, the master device will

override the acknowledge bit by pulling the data line high

during the low period before the ninth clock pulse. This is

known as no acknowledge. The master will then take the

data line low during the low period before the tenth clock

pulse, then high during the tenth clock pulse to assert a stop

condition.

Any number of bytes of data may be transferred over the

serial bus in one operation, but it is not possible to mix read

and write in one operation because the type of operation is

determined at the beginning and cannot subsequently be

changed without starting a new operation. In the case of the

ADT7481, write operations contain either one or two bytes,

while read operations contain one byte.

To write data to one of the device data registers or to read

data from it, the address pointer register must be set so that

the correct data register is addressed. The first byte of a write

operation always contains a valid address that is stored in the

address pointer register. If data is to be written to the device,

the write operation contains a second data byte that is written

to the register selected by the address pointer register.

This procedure is illustrated in Figure 15. The device

address is sent over the bus followed by R/W

set to 0 and

followed by two data bytes. The first data byte is the address

of the internal data register to be written to, which is stored

in the address pointer register. The second data byte is the

data to be written to the internal data register.

Figure 15. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

SCLK

SDATA

D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY

ADT7481

START BY

MASTER

ACK. BY

ADT7481

D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY

ADT7481

STOP BY

MASTER

SCLK (CONTINUED)

SDATA (CONTINUED)

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

FRAME 3

DATA BYTE

R/W

Figure 16. Writing to the Address Pointer Register Only

SCLK

SDATA

D5 D4 D3 D2 D1 D0

ACK. BY

ADT7481

STOP BY

MASTER

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

ACK. BY

ADT7481

R/W

Figure 17. Reading Data from a Previously Selected Register

SCLK

SDATA

D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY

ADT7481

STOP BY

MASTER

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

DATA BYTE FROM ADT7481

ACK. BY

ADT7481

R/W

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